发明名称 Hysteresis characteristic input circuit including resistors capable of suppressing penetration current
摘要 In a hysteresis characteristic input circuit, first and second resistors are connected in parallel between a first power supply terminal and a connection point, and first and second MOS transistors are connected in parallel between the connection point and a second power supply terminal and are controlled by an input voltage. An inverter has an input connected to the connection point and an output adapted to generate an output voltage. A first switching element is connected in series to the second resistor, and a second switching element is connected in series to the second MOS transistor. The first and second switching elements are complementarily controlled by the output voltage.
申请公布号 US7683687(B2) 申请公布日期 2010.03.23
申请号 US20070979697 申请日期 2007.11.07
申请人 NEC ELECTRONICS CORPORATION 发明人 KAWASHIMA SHINJI;DOI KAZUNORI
分类号 H03K3/00 主分类号 H03K3/00
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