GATED CLOCK CELL, SCAN TEST CONTROL CIRCUIT, AND METHOD FOR DESIGNING RTL LEVEL OF SCAN TEST CONTROL CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a means for avoiding an increase in test power by stopping an operation clock partially during scanning during which a clock is generally unable to be stopped. SOLUTION: A scan power control terminal and an accompanying function are added to a gated clock cell which controls a clock tree. A scan power control circuit 3003 is added to a scan test control circuit 3000 which is a gathering of gated clocks, allowing the operation of the gated clock cell equipped with the scan power control terminal to be controlled. During a scan test, a specific gated clock cell equipped with the scan power control terminal is stopped (operated) using the scan power control circuit 3003, thereby performing a scan test without test division. COPYRIGHT: (C)2010,JPO&INPIT