发明名称 |
METHOD AND APPARATUS FOR INSTRUCTION SET ARCHITECTURE TO PERFORM PRIMARY AND SHADOW DIGITAL SIGNAL PROCESSING SUB-INSTRUCTIONS SIMULTANEOUSLY |
摘要 |
<p>Disclosed is a method, apparatus, and an instruction set architecture (ISA) for an application specific signal processor (ASSP) tailored to digital signal processing (DSP) applications. A single DSP instruction includes a pair of sub-instructions: a primary DSP sub-instruction and a shadow DSP sub-instruction. Both the primary and the shadow DSP sub-instructions are dyadic DSP instructions performing two operations in one instruction cycle. Each signal processing unit of the ASSP includes a primary stage to execute a primary DSP sub-instruction based upon current data and a shadow stage to simultaneously execute a shadow DSP sub-instruction based upon delayed data stored locally within registers of the signal processing units. The present invention efficiently executes DSP instructions by simultaneously executing primary DSP sub-instructions (based upon current data) and shadow DSP sub-instructions (based upon delayed locally stored data) with a single DSP instruction.</p> |
申请公布号 |
EP1323030(B1) |
申请公布日期 |
2010.03.17 |
申请号 |
EP20010964189 |
申请日期 |
2001.08.16 |
申请人 |
INTEL CORPORATION |
发明人 |
GANAPATHY, KUMAR;KANAPATHIPILLAI, RUBAN |
分类号 |
G06F9/30;G06F7/52;G06F7/53;G06F7/533;G06F7/544;G06F9/302;G06F9/318;G06F9/38;G06F17/10 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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