发明名称 Testing Circuit Split Between Tiers of Through Silicon Stacking Chips
摘要 A method of testing a die having a non-testable circuit, where the non-testable circuit is logically incomplete and forms part of a logically complete multiple tier circuit. The method includes reconfiguring a tier-to-tier input point or tier-to-tier output point associated with a primary path of the non-testable circuit to create a logically complete secondary path for the tier-to-tier point such that the non-testable circuit can be tested. Testable dies and methods of preparing such dies are also provided.
申请公布号 US2010060312(A1) 申请公布日期 2010.03.11
申请号 US20080206977 申请日期 2008.09.09
申请人 QUALCOMM INCORPORATED 发明人 TOMS THOMAS R.
分类号 G01R31/3185;H03K19/00 主分类号 G01R31/3185
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