MICROPROCESSOR WITH PIPELINE BUBBLE DETECTION DEVICE

摘要

Microprocessor, comprising a pipeline microarchitecture (1) and a pipeline bubble detection device (2), wherein the pipeline bubble detection device (2) comprises a minimum processing timing cycle determination unit (3) for determining a minimum and/or optimum number of processing timing cycles of one or more program commands, said cycles running through the pipeline microarchitecture (1) and/or being processed thereby.