发明名称 |
THE CIRCUIT AND CONTROL METHOD FOR TRANSMITTING AND RECEIVING DATA |
摘要 |
PURPOSE: A circuit and a control method for transmitting and receiving data are provided to constantly maintain the margin of parallel data by deciding the frequency of a clock based on CAS Latency and time-dividing the parallel data. CONSTITUTION: Delay units(507, 509) output a delay control signal by responding to CAS latency and delaying a control signal. An output driver unit(503) transmits time-divided parallel data for writing in response to the control signal and the delay control signal. A latch unit(505) receives and arranges the transmitted parallel data by the output driver unit in response to the control signal and the delay control signal. The bit number of the parallel data transmitted by the output driver unit is the half number of the parallel data which the output driver unit and the latch unit transmit and receive.
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申请公布号 |
KR20100026729(A) |
申请公布日期 |
2010.03.10 |
申请号 |
KR20080085850 |
申请日期 |
2008.09.01 |
申请人 |
HYNIX SEMICONDUCTOR INC. |
发明人 |
SHIN, SUN HYE;HA, SUNG JOO |
分类号 |
G11C11/4093;G11C11/407;G11C11/4096 |
主分类号 |
G11C11/4093 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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