| 摘要 |
A processor, such as a superscalar processor, is responsive to a stream of program instructions to issue said program instructions under control of dynamic scheduling circuitry to respective execution units for execution. At least one of the execution units includes error detecting circuitry for detecting a change in an output signal which occurs after the output signal has latched and during an error detecting period following said latching. The scheduling circuitry is arranged to suppress issue of program instructions to an execution unit having such error detecting circuitry on consecutive processing cycles, so as to avoid short path errors resulting from false positive error detection arising due to a signal path through the execution unit that is too quick. The error detecting circuitry is also responsive to a change in a signal generated by an error-detecting execution unit during the error detecting period to trigger an error recovery response. |
