发明名称 Integrated circuit architecture for testing variable delay circuit
摘要 An integrated circuit is provided with first and second variable delay circuits, a test data feeding circuitry, a test control circuit, and a wire-connection line. The test data feeding circuitry feeds first and second test data signals to the first and second variable delay circuits, respectively. The first and second test data signals are complement to each other. The test control circuit feeds first and second drive capability control signals to the first and second variable delay circuits to control drive capabilities of the first and second variable delay circuits. The wire-connection line provides a wire-connection for outputs of the first and second variable delay circuits.
申请公布号 US2010052698(A1) 申请公布日期 2010.03.04
申请号 US20090461853 申请日期 2009.08.26
申请人 NEC ELECTRONICS CORPORATION 发明人 IWASHITA TOORU;SHIHARA MASAHIKO;TANGODA ATSUSHI
分类号 G01R27/28 主分类号 G01R27/28
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