发明名称 SELECTION SYSTEM OF PLURALITY OF BUSES AND PROGRAMMABLE CONTROLLER WITH THE SYSTEM
摘要 <P>PROBLEM TO BE SOLVED: To easily construct a control system at low cost without requiring a user to be conscious of bus specifications when constructing the control system by mixing a plurality of PLC buses each having a different bus specification and connecting various modules to the buses. Ž<P>SOLUTION: The system includes a CPU 2, an FPGA (Field Programmable Gate Array) 8, and the plurality of PLC buses 9-11. The FPGA 8 has a circuit configuration operating such that one of the plurality of PLC buses 9-11 is selected according to sequence program execution of the CPU 2. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2010049508(A) 申请公布日期 2010.03.04
申请号 JP20080213491 申请日期 2008.08.22
申请人 KOYO ELECTRONICS IND CO LTD 发明人 YOKOO MASAHIKO
分类号 G05B19/05 主分类号 G05B19/05
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