发明名称 |
INTEGRATED CIRCUIT WITH BIT LINES POSITIONED IN DIFFERENT PLANES |
摘要 |
An integrated circuit includes a memory cell array including a plurality of memory cells. A first plurality of bit lines is positioned in a first plane. The first plurality of bit lines is electrically coupled to a first set of the memory cells. A second plurality of bit lines is positioned in a second plane that is different than the first plane. The second plurality of bit lines is electrically coupled to a second set of the memory cells.
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申请公布号 |
US2010039845(A1) |
申请公布日期 |
2010.02.18 |
申请号 |
US20080193267 |
申请日期 |
2008.08.18 |
申请人 |
VOLLRATH JOERG;GNAT MARCIN |
发明人 |
VOLLRATH JOERG;GNAT MARCIN |
分类号 |
G11C5/02;G11C5/06;G11C7/06;G11C11/24 |
主分类号 |
G11C5/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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