发明名称 Semiconductor device and manufacturing method thereof for reducing the area of the memory cell region
摘要 A structure is adopted for a layout of an SRAM cell which provides a local wiring 3a between a gate 2a and gate 2b and connects an active region 1a and an active region 1b. This eliminates the necessity for providing a contact between the gate 2a and the gate 2b. Therefore, it is possible to reduce the size of a memory cell region C in a short side direction. Furthermore, a structure whereby a left end of a gate 2c is retreated from the gate 2a and a local wiring 3b which connects the active region 1b and gate 2c disposed in a diagonal direction is adopted. This allows the gate 2a to be shifted toward the center of the memory cell region C.
申请公布号 US7663193(B2) 申请公布日期 2010.02.16
申请号 US20080237693 申请日期 2008.09.25
申请人 RENESAS TECHNOLOGY CORP. 发明人 TSUBOI NOBUO;IGARASHI MOTOSHIGE
分类号 H01L21/00 主分类号 H01L21/00
代理机构 代理人
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