发明名称 INSTRUCTION OPERATION CODE GENERATION SYSTEM
摘要 It is possible to increase the processor instruction set design job efficiency and reduce workload on designers in investigation of an instruction set. An instruction operation code generation system includes an operation code bit width decision means, an instruction sorting means, and an operation code value decision means. The operation code bit width decision means decides a bit width that can be assigned for an operation code of each instruction according to specification data associated with a processor instruction set. The instruction sorting means sorts the instructions according to the operation code bit width. The operation code value decision means decides the value of the operation code of each instruction.
申请公布号 US2010037039(A1) 申请公布日期 2010.02.11
申请号 US20070515439 申请日期 2007.11.19
申请人 发明人 KUMURA TAKAHIRO
分类号 G06F9/30;G06F9/06;G06F15/76 主分类号 G06F9/30
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