发明名称 |
WIRELESS COMMUNICATION DEVICE, INTEGRATED CIRCUIT AND METHOD OF TIMING SYNCHRONISATION |
摘要 |
A wireless communication device comprises a first sub-system arranged to pass data to a second sub-system comprising timing synchronisation logic operably coupled to a counter, such that data is sampled by the timing synchronisation logic when passed to the second sub-system from the first sub-system wherein the wireless communication device is characterised in that the timing synchronisation logic is arranged to determine a position of a first data frame and in response thereto initiate a counting process of the counter and determine a position of a second data frame and in response thereto determine a count value from the counting process of the counter and in response to the count value determine whether to initiate a timing advance or timing retard operation on the data being passed to the second sub-system. In this manner, the inventive concept provides the wireless communication device with a mechanism to achieve timing synchronisation. In particular, the inventive concept may allow a radio frequency integrated circuit to implement timing synchronisation by advancing or retarding an 'actual' signal sent from digital baseband circuits in a 3G DigRF wireless communication device. |
申请公布号 |
US2010034192(A1) |
申请公布日期 |
2010.02.11 |
申请号 |
US20070521862 |
申请日期 |
2007.01.02 |
申请人 |
FREESCALE SEMICONDUCTOR, INC. |
发明人 |
BEAMISH NORMAN;KELLEHER PAUL;SCHWARTZ DANIEL B. |
分类号 |
H04J3/06 |
主分类号 |
H04J3/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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