发明名称 Structure and method for reducing miller capacitance in field effect transistors
摘要 A method for forming a field effect transistor (FET) device includes forming a gate conductor and gate dielectric on an active device area of a semiconductor wafer, the semiconductor wafer including a buried insulator layer formed over a bulk substrate and a semiconductor-on-insulator layer initially formed over the buried insulator layer. Source and drain extensions are formed in the semiconductor-on-insulator layer, adjacent opposing sides of the gate conductor, and source and drain sidewall spacers are formed adjacent the gate conductor. Remaining portions of the semiconductor-on-insulator layer adjacent the sidewall spacers and are removed so as to expose portions of the buried insulator layer. The exposed portions of the buried insulator layer are removed so as to expose portions of the bulk substrate. A semiconductor layer is epitaxially grown on the exposed portions of the bulk substrate and the source and drain extensions, and source and drain implants are formed in the epitaxially grown layer.
申请公布号 US7659172(B2) 申请公布日期 2010.02.09
申请号 US20050164343 申请日期 2005.11.18
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION;ADVANCED MICRO DEVICES, INC. (AMD) 发明人 NAYFEH HASAN M.;WAITE ANDREW
分类号 H01L21/336 主分类号 H01L21/336
代理机构 代理人
主权项
地址