发明名称 |
Self-synchronizing bit error analyzer and circuit |
摘要 |
A self-synchronizing data bus analyzer is provided which can include a generator linear feedback shift register (LFSR) to generate a first data set, and can include a receiver LFSR to generate a second data set. The data bus analyzer may also include a bit sampler to sample the first data set received through a data bus coupled to the generator LFSR and output a sampled first data set. A comparator can be included to compare the sampled first data set with the second data set generated by the receiver LFSR and provide a signal to the receiver LFSR to adjust a phase of the receiver LFSR until the second data set is substantially the same as the first data set.
|
申请公布号 |
US7661039(B2) |
申请公布日期 |
2010.02.09 |
申请号 |
US20080154188 |
申请日期 |
2008.05.21 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BOUDON GERARD;MALCAVET DIDIER;PEREIRA DAVID;STEIMLE ANDRE |
分类号 |
G06F11/00 |
主分类号 |
G06F11/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|