| 摘要 |
A computer comprises a main TLB for holding a plurality of address translation pairs indicating the correspondence of a virtual address and an absolute address as a page table and a micro TLB for holding part of the page table held in the main TLB. The micro TLB registers a TLB virtual address[63:13]and a TLB absolute address[46:13]in association with each other. In this configuration, the computer chops the page table into a page size of 8K or 4M to register them in the micro TLB at the time of registration in the micro TLB. The computer, when receiving an address translation request, searches the address on the basis of any of the page size of 8K or 4M registered in the micro TLB. Thus, address comparison conditions can be reduced to improve the processing performance.
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