| 摘要 |
A system having a plurality of memory cells organized in rows and columns. Each column includes upper and lower sets of memory cells connected to corresponding common upper/lower bit lines. Each column includes an evaluation circuit coupled to the upper and lower bit lines and configured to evaluate signals on these bit lines and to produce an output signal. Each of the upper and lower bit lines has an associated bit line delay, one of which is greater than the other. The evaluation circuit has first and second inputs which have associated evaluation delays, one of which is greater than the other. In each column, the bit line having the greater bit line delay is connected to the evaluation circuit input having the smaller evaluation delay, and the bit line having the smaller bit line delay is connected to the evaluation circuit input having the greater evaluation delay.
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