<p>A semiconductor integrated circuit the logic circuits of which are duplexed is provided with a comparison circuit for outputting the result of the comparison of whether or not the output value of each of the logic circuits is matched with each other. A storage circuit of each of the logic circuits is supplied with clock signals which repeat first periods and second periods alternately and in which the start of the first period of each of the clock signals is matched with one another and the end of the second period thereof is matched with one another. Among the clock signals, at least one clock signal has different length in the first period and the second period and at least one clock signal has a signal pattern different from the signal patterns of the other clock signals.</p>
