| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To simplify layout of a transfer transistor and an electric conductor for connection. <P>SOLUTION: The NAND flash memory is provided with: a memory cell array 11 comprised of first, second, and third NAND blocks BK1, BK2, BK3 disposed in order in a first direction; first and second transfer transistor blocks 21 disposed in order in the first direction at a second direction crossing the first direction of the memory cell array 11. An address allocation to a plurality of word lines WL0-WL7 in the first NAND block BK1 is inverted against an address allocation to the plurality of word lines WL0-WL7 in the third NAND block BK3. <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
