发明名称 Generating a pulse signal with a modulated duty cycle
摘要 Generating an output pulse signal (Y), which has an output signal period (Ty), which is divided by a magnitude transition into a leading part (LP) and a trailing part (TP). During each output signal period (Ty) altering means (27 to 36) determine in a coarse and fine way a duration (TLP, TTP) of one or both of said output signal period parts (LP, TP) by using a clock signal (Cx) of different clock cycle durations (TCx0, TCx1, TCx2), dependent on a value of a first digital number (D1) and a value of second, less significant digital number (D3, D5), respectively.
申请公布号 US7656213(B2) 申请公布日期 2010.02.02
申请号 US20060066513 申请日期 2006.09.12
申请人 KONINKLIJKE PHILIPS ELECTRONICS, N.V. 发明人 DEPPE CARSTEN;HATTRUP CHRISTIAN
分类号 H03K3/00;H03K7/08 主分类号 H03K3/00
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