发明名称 |
Dual clock domain deskew circuit |
摘要 |
In general, in one aspect, the disclosure describes an apparatus including a first deskew unit and a second deskew unit. The first deskew unit operates at a first clock domain and provides fine timing adjustment to a signal. The second deskew unit operates at a second clock domain that is slower than the first clock domain and provide coarse timing adjustment to the signal.
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申请公布号 |
US7656983(B2) |
申请公布日期 |
2010.02.02 |
申请号 |
US20060541427 |
申请日期 |
2006.09.29 |
申请人 |
INTEL CORPORATION |
发明人 |
KLOWDEN DANIEL S.;KUMAR S. REJI;PANIKKAR ADARSH;VAKIL KERSI H.;KOLLA ABHIMANYU |
分类号 |
H04L7/00;H04L25/00;H04L25/40 |
主分类号 |
H04L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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