| 摘要 |
To provide a memory system that can store data smaller than a block size and data larger than the block size without deteriorating writing efficiency, and can dynamically change a parallelism according to the data. The memory system according to an embodiment of the present invention comprises a DRAM 11, a NAND memory 12, and a controller having a NAND-controller control register 150 that specifies parallel-operating element specifying information indicating parallel operating elements 120A to 120D in the NAND memory 12 to be used at the time of data access and an address of data with respect to a NAND interface 140, the NAND interface 140 connected in parallel to the respective parallel operating elements 120A to 120D for accessing the address of one or a plurality of parallel operating elements 120A to 120D selected based on the specified parallel-operating element specifying information and the address, and a CPU 131 that sets the parallel-operating element specifying information in the NAND-controller control register 150 according to the type of data to be accessed.
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