Semiconductor Device Layout Including Cell Layout Having Restricted Gate Electrode Level Layout with Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing with Corresponding Non-Symmetric Diffusion Regions

摘要

A restricted layout region includes a diffusion level layout including p-type and n-type diffusion region layout shapes separated by a central inactive region. The diffusion region layout shapes are defined in a non-symmetrical manner relative to a centerline defined to bisect the diffusion level layout. A gate electrode level layout is defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level layout includes linear-shaped layout features defined along at least four different lines of extent in the first parallel direction. The restricted layout region corresponds to an entire gate electrode level of a cell layout.