SEMICONDUCTOR MEMORY DEVICE

摘要

PROBLEM TO BE SOLVED: To increase a speed of a clock frequency in a semiconductor memory device configured to perform a clock synchronous burst read operation.

SOLUTION: When a buffer memory 21a constituted of one bank is determined as a read target to execute the clock synchronous burst read operation and a start address STADD is a last column address, a burst read control circuit 41 starts counting up a SRAM address MEMADD in a cycle (a first clock) before reaching a read latency cycle (a fourth clock), and latches first read data D3 of a first word to the data latch (A) 281. A row address is switched to start reading of read data D4 of a second word.

COPYRIGHT: (C)2010,JPO&INPIT