发明名称 |
Delay line circuit for generating a fixed delay |
摘要 |
A delay line circuit is provided. The delay line circuit includes a reference voltage generating circuit that generates a reference voltage, the reference voltage having a positive temperature coefficient. The delay line circuit also includes a voltage regulating circuit that generates a regulated voltage in response to the generated reference voltage as an input, and a delay chain circuit coupled to the voltage regulator to receive the regulated voltage, the delay chain circuit outputting a delay signal. In an embodiment consistent with the present invention, the reference voltage generating circuit includes a bandgap reference voltage circuit. In another embodiment consistent with the present invention, the reference voltage generating circuit includes a proportional to absolute temperature (PTAT) circuit.
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申请公布号 |
US2010007397(A1) |
申请公布日期 |
2010.01.14 |
申请号 |
US20080218457 |
申请日期 |
2008.07.11 |
申请人 |
INTEGRATED DEVICE TECHNOLOGY, INC. |
发明人 |
ZHANG SHENGYUAN;WANG YONG;WANG YANBO |
分类号 |
H03H11/26;G05F1/00;H03K3/011 |
主分类号 |
H03H11/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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