发明名称 |
NOR FLASH MEMORY ARRAY WITH VERTICAL CHANNEL BUILTIN FIN-SPLIT LAYER |
摘要 |
<p>PURPOSE: A NOR flash memory array of a vertical channel embedding a fin separation layer is provided to prevent a leakage current between bit lines by arranging the pin separation layer between the silicon fins. CONSTITUTION: A NOR flash memory array includes a silicon substrate(10), a charge storage(60), and a gate line(70). The silicon substrate has the silicon fins(12a,12b). The charge storage is arranged on the silicon fins. The gate lines are positioned on the charge storage and cross the silicon fins. The NOR flash memory array includes a fin separation layer(11). The fin separation layer is arranged between the silicon fins.</p> |
申请公布号 |
KR20100003923(A) |
申请公布日期 |
2010.01.12 |
申请号 |
KR20080063980 |
申请日期 |
2008.07.02 |
申请人 |
SEOUL NATIONAL UNIVERSITY INDUSTRY FOUNDATION |
发明人 |
PARK, BYUNG GOOK;YUN, JANG GN |
分类号 |
H01L27/115;H01L29/78 |
主分类号 |
H01L27/115 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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