发明名称 |
F-SRAM Margin Screen |
摘要 |
A process of testing an integrated circuit containing a programmable data storage component containing at least two ferroelectric capacitors coupled to complementary state nodes that includes applying a disturb voltage prior to a recall operation. Also, a process of testing an integrated circuit containing a programmable data storage component containing at least two ferroelectric capacitors coupled to complementary state nodes that includes adjusting a disturb voltage and determining if a screening data value and a read data value meet a criterion for determining a limiting disturb voltage.
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申请公布号 |
US2010002488(A1) |
申请公布日期 |
2010.01.07 |
申请号 |
US20090491817 |
申请日期 |
2009.06.25 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
RODRIGUEZ JOHN A.;MCADAMS HUGH P.;SUMMERFELT SCOTT R.;BARTLING STEVEN |
分类号 |
G11C11/22;G11C5/14;G11C11/24;G11C29/00 |
主分类号 |
G11C11/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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