发明名称 CIRCUIT RESISTANCE CONTRACTION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a circuit resistance contraction method capable of improving the working efficiency of EM inspection by preventing the occurrence of pseudo-errors. Ž<P>SOLUTION: In each wiring layer M1, M2, a plurality of wiring resistances RM1, RM2 divided by a plurality of via holes VH are made to contract by two wiring resistors RM11, RM21 each having equivalent value which are connected in series, and corresponding mutual median points of the respective wiring layers are short-circuited and serves as node n45. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2010002965(A) 申请公布日期 2010.01.07
申请号 JP20080158965 申请日期 2008.06.18
申请人 RENESAS TECHNOLOGY CORP 发明人 SATO YOHEI;YASUDA TAKASHI;TOMOEDA NORIKO
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
代理机构 代理人
主权项
地址