| 摘要 |
An n−type semiconductor region is provided with an n−diffusion region serving as a drain region, and at one side of the n−diffusion region a p diffusion region and an n+ diffusion region serving as a source region are provided. At an other side of the n−diffusion region a trench is provided and has an insulator introduced therein. Immediately under the n−diffusion region a p−buried layer is provided. In a region of the n−semiconductor region an n+ diffusion region to which a high potential is applied is provided and electrically connected to the n−diffusion region by an interconnect having a resistor. On a surface of a portion of the p diffusion region that is sandwiched between the n+ diffusion region and the n−diffusion region a gate electrode is provided, with a gate insulation film posed therebetween. |
