发明名称 STACKED ESD PROTECTION CIRCUIT HAVING REDUCED TRIGGER VOLTAGE
摘要 A stacked gate-coupled N-channel field effect transistor (GCNFET) electrostatic discharge (ESD) protection circuit involves a stack of stages. Each stage has an NFET whose body is coupled to its source. A resistor is coupled between the gate and the source. A current path is provided from a supply voltage node to the gate of each NFET such that during an ESD event, a current will flow across the resistor of the stage and induce triggering. In one embodiment, an NFET stage that is isolated from the supply voltage node by and other stage has an associated capacitance structure. During the transient voltage condition of the ESD event, current flows from the supply voltage node, through the capacitance structure and to the gate, and then through the resistor, thereby initiating triggering. The GCNFET ESD protection circuit has a trigger voltage that is less than twenty percent higher than its holding voltage.
申请公布号 EP2140491(A1) 申请公布日期 2010.01.06
申请号 EP20080745774 申请日期 2008.04.14
申请人 QUALCOMM INCORPORATED 发明人 WORLEY, EUGENE
分类号 H01L27/02;H02H9/04 主分类号 H01L27/02
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