发明名称 |
Phase-locked loop start-up techniques |
摘要 |
Implementations feature systems and techniques for phase-locked loops (PLLs). In some aspects, implementations feature a system that has a PLL circuit including an oscillator and programmable reference frequency divider circuit or a programmable feedback frequency divider circuit. The PLL includes a control circuit to reduce a time required for a PLL settling time by programming a division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit to target the oscillator to operate outside of a system operating frequency range of the oscillator during start-up of PLL operations. The control circuit can program another division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit after stabilization of the variable oscillator.
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申请公布号 |
US7639088(B2) |
申请公布日期 |
2009.12.29 |
申请号 |
US20080110048 |
申请日期 |
2008.04.25 |
申请人 |
NANOAMP MOBILE, INC. |
发明人 |
SHEN DAVID H.;SHEN ANN P.;SCHUUR AXEL |
分类号 |
H03L7/10;H03L7/18;H04B1/00 |
主分类号 |
H03L7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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