发明名称 DISCRETE DELAY LINE FOR PULSE SIGNALS
摘要 FIELD: physics; control. ^ SUBSTANCE: invention relates to pulse, digital engineering and can be used in computers, automation, measuring devices, radar, communication devices etc, for making a discrete line for delaying output pulses relative input pulses within its duration limits in accordance with an incoming binary code. The device has an inverter gate (3), multiplexer (MX) (5), the input of which is connected to the input (6) which blocks/allows generation of output pulses of pulse generator (8). The output of pulse generator (8) is connected to the complementing input of an n-bit pulse counter (9), n outputs which are connected to n inputs of a digital comparator (K) (10), the other n inputs of which are connected to n outputs of an n-bit register (11), which assigns the code value required for delaying input pulse signals. The output of the comparison result of K (10) is connected to the complementing input of an output single-bit pulse counter (12), one of the outputs of which is connected to the control input of MX (5). The said delay line is distinguished by employing a binary counter as a generator of the time intervals for delaying the front and droop of the input sequence, which, coupled with delay of fronts and drooping of input pulses, allows for making a compact integrated circuit of quasicontinuous delay line for input pulses. ^ EFFECT: reduced area occupied by the integrated circuit; minimum possible nanosecond increment value of the delay line. ^ 2 dwg
申请公布号 RU2377717(C1) 申请公布日期 2009.12.27
申请号 RU20080118779 申请日期 2008.05.12
申请人 IVANOV ALEKSANDR IOSIFOVICH;IVANOV VLADIMIR ALEKSANDROVICH 发明人 IVANOV ALEKSANDR IOSIFOVICH;IVANOV VLADIMIR ALEKSANDROVICH
分类号 H03H7/30;H03K5/13 主分类号 H03H7/30
代理机构 代理人
主权项
地址
您可能感兴趣的专利