| 摘要 |
The present invention relates to a DPLL (300, 400) having a P2D (60) with an enhanced BBPD. Such a P2D (60) comprises a BBPD (62), an additional digital circuit (200) including a sign detector (210), a counter (220) and a mapping function (230), and a summer block (64). During the locking process, the BBPD (62) may output a repeating value, namely a string of data bits of same polarity value either "+1" or "-1". The polarity sign is detected by the sign detector (210), and the data string length is determined by the counter (220) that is reset to zero whenever the BBPD output changes sign. The mapping function (230) is configured for mapping the data string length in input to the phase correction level in output. Its output is added to that of the BBPD (62) through the summer block (64), such that the phase correction level is increased to enhance the locking process whenever a data string is detected. |
