| 摘要 |
<P>PROBLEM TO BE SOLVED: To hide a penalty for a load when calling distributed display lists to increase image processing speed. Ž<P>SOLUTION: A preceding stage analysis circuit 4g prefetches and sequentially analyzes a main display list 6, and extracts a jump instruction. A bus control circuit 4j acquires a sub-display list 10 corresponding to the jump instruction extracted by the preceding stage analysis circuit 4g through a CG bus interface 4e. A subsequent stage analysis circuit 4h sequentially analyzes the main display list 6, and sequentially outputs an instruction to an image processing part based on the analysis result thereof. The subsequent analysis circuit 4h analyzes the sub-display list 10 acquired by the bus control circuit 4j as a part of the main display list 6, in a jump portion including the jump instruction of the main display list 6. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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