发明名称 |
Method and Apparatus for Wafer Level Integration Using Tapered Vias |
摘要 |
A semiconductor device has first and second wafers having bond pads. The bond pad of the second wafer is connected to the bond pad of the first wafer using a conductive adhesive. A first interconnect structure is formed within the second wafer and includes a first via formed in a back surface of the second wafer to expose the bond pad of the second wafer. A first metal layer is formed conformally over the first via and is in electrical contact with the bond pad of the second wafer. A third wafer is mounted over the second wafer by connecting a bond pad formed over a front surface of the third wafer to the first metal layer. A second interconnect structure is formed over a backside of the third wafer opposite the front surface. The second interconnect structure is electrically connected to the first metal layer. |
申请公布号 |
US2009309235(A1) |
申请公布日期 |
2009.12.17 |
申请号 |
US20080137242 |
申请日期 |
2008.06.11 |
申请人 |
STATS CHIPPAC, LTD. |
发明人 |
SUTHIWONGSUNTHORN NATHAPONG;MARIMUTHU PANDI CHELVAM |
分类号 |
H01L23/52;H01L21/00 |
主分类号 |
H01L23/52 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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