发明名称 |
Silicide gate transistors and method of manufacture |
摘要 |
A method in which a gate and raised source/drain (S/D) regions are fully silicided in separate steps to avoid degrading the resistance or junction leakage is described. A gate dielectric layer, gate, and spacers are formed over a semiconductor layer that is preferably Si, SiGe, or SiGeC on a buried insulator. Raised S/D regions are formed by selective epitaxy between spacers and isolation regions. The gate is protected with a mask while the raised S/D regions are covered with a first metal layer. A first anneal affords fully silicided S/D regions. A dielectric stack is deposited on the substrate and planarized to be coplanar with the top of the spacers. The mask is removed and a second metal layer is deposited. A second anneal yields a fully silicided gate electrode. The invention is also an SOI transistor with silicided raised S/D regions and a fully silicided and optionally recessed gate.
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申请公布号 |
US7633127(B2) |
申请公布日期 |
2009.12.15 |
申请号 |
US20060381649 |
申请日期 |
2006.05.04 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY |
发明人 |
WEN CHENG-KUO;YEO YEE-CHIA;TSAO HSUN-CHIH |
分类号 |
H01L23/62;H01L21/336;H01L21/8238;H01L21/84;H01L27/12;H01L29/45;H01L29/49;H01L31/0392 |
主分类号 |
H01L23/62 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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