发明名称 CORRELATED DOUBLE SAMPLING CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a correlated double sampling circuit extracting a signal component with a high S/N ratio by achieving a low noise characteristic without causing an increase in a circuit scale and power consumption. Ž<P>SOLUTION: A first switch S1 and a hold capacitor Ch are connected in series between an inverted input terminal of an operational amplifier A1 and an output terminal of the operational amplifier A1. Then, the hold capacitor Ch is made to hold only electric charge of a phase 2 by turning off the first switch S1 in a phase 1 (first sampling period), and turning on the first switch S1 in the phase 2 (second sampling period). Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2009290439(A) 申请公布日期 2009.12.10
申请号 JP20080139445 申请日期 2008.05.28
申请人 ASAHI KASEI ELECTRONICS CO LTD 发明人 SHIMATAKA NAOTO
分类号 H04N5/335;H04N5/357;H04N5/363;H04N5/378 主分类号 H04N5/335
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