| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce power consumption in a buffer memory device for compensating the speed (operation frequency) difference of data transmission and processing. Ž<P>SOLUTION: In the buffer memory device 1 for compensating the difference of the operation frequency by interposing three line memories M1-M3 between a scanner 2 and an image processing circuit 4 and making the write speed and read speed of the line memories M1-M3 be different, a comparator 13 for detecting the change in the data of the corresponding (same) address (pixel) of the consecutive lines is provided, and only when there is the change, write to the line memory of the first stage is permitted or a shift operation to the post stage side (the write operation of the line memory of the next stage) is permitted (write access is performed). Thus, when there is no change, since the write operation to a memory cell or the shift operation is not performed, the power consumption by the memory cell is reduced. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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