| 摘要 |
"Negative And" (NAND) logic gate metal oxide semiconductor field effect transistor (MOSFET) switch(es) incorporated in the first stage of a "pseudo" current mode logic (CML) latch to provide a low-resistance (or high-resistance) circuit path to the output depending on the input voltage. This/these switch(es) are also used to deactivate the first stage of the circuit during the second half of a timing clock cycle, so as to permit the first stage to be activated only during the first half of a clock cycle. "Cross-coupled" inverter(s) are also used in the second stage of the circuit to provide acceptable "rail-to-rail" output voltage differential "swing" using less current. In addition, the second stage also has MOSFET switch(es) which activate only during the second half of a timing clock cycle and are deactivated during the first half of a clock cycle, which requires use of less current and thus reduces power consumption.
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