发明名称 DATA PROCESSOR, MEMORY CONTROLLER, AND ITS ACCESS CONTROL METHOD
摘要 PROBLEM TO BE SOLVED: To solve the problem that it is not possible to sufficiently quicken an operating speed in the write-in operation of partial data in a conventional data processor. SOLUTION: This data processor is provided with: a memory 20 for inputting/outputting data with prescribed data width; an arithmetic circuit 10 for performing access to the memory 20 by outputting a read instruction or a write instruction; and an access control circuit 30 for, when receiving the write instruction and partial data associated with the write instruction from the arithmetic circuit 10, replacing a part of the first read data read from the memory 20 with the partial data, and for outputting write data to the memory 20. When the write instruction is output corresponding to the read instruction output prior to the write instruction, the access control circuit 30 replaces a part of the second read data which have already been acquired in response to the previously output read instruction with the partial data instead of the first read data, and outputs the write data. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2009289170(A) 申请公布日期 2009.12.10
申请号 JP20080143182 申请日期 2008.05.30
申请人 NEC ELECTRONICS CORP 发明人 IKEUCHI TORU;AKAIKE YUKIHIKO
分类号 G06F12/04;G06F12/16 主分类号 G06F12/04
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