发明名称 WIRING SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME
摘要 <P>PROBLEM TO BE SOLVED: To provide a wiring substrate with high reliability in interlayer connection, and reduced in variation in connection resistance values by making the formation of minute wiring and the securement of interlayer connection. Ž<P>SOLUTION: The wiring substrate includes an electrically insulating base material 101, wiring placed on both sides of the electrically insulating base material 101, a via hole 103 formed by penetrating the electrically insulating base material 101, and a conductive body 104 filled in the via hole 103. The wiring at each side of the electrically insulating base material 101 is electrically connected to each other by the conductive body 104. At least one of the wiring is thin membrane wiring 102 formed by a vacuum membrane formation method. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2009290233(A) 申请公布日期 2009.12.10
申请号 JP20090205482 申请日期 2009.09.07
申请人 PANASONIC CORP 发明人 HIGASHITANI HIDEKI;ANPO TAKEO
分类号 H05K1/11;H05K3/18;H05K3/40 主分类号 H05K1/11
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