发明名称 NANOWIRE CIRCUIT ARCHITECTURE
摘要 A nanowire circuit architecture is presented. The technology comprises of nanowire transistors (8,9), and optionally nanowire capacitors (12) and nanowire resistors (11), that are integrated using two levels of interconnects only (1,2). Implementations of ring-oscillators, sample-and-hold circuits, and comparators may be realized in this nanowire circuit architecture. Circuit input and circuit output as well as the transistor connections within each circuit are provided in the two levels of interconnects (1,2).
申请公布号 KR20090126311(A) 申请公布日期 2009.12.08
申请号 KR20097022548 申请日期 2008.03.28
申请人 QUNANO AB 发明人 WERNERSSON LARS ERIK
分类号 B82B1/00;H01L29/08;H01L29/78 主分类号 B82B1/00
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