发明名称 Multi-thread FIFO memory generator
摘要 Systems and methods for generating synthesizable code representing first-in first-out (FIFO) memories may be used to produce FIFO memories for multi-threaded processing. A single FIFO memory is shared between the threads to conserve die area, however each thread may be executed independently, as if each thread has a dedicated FIFO memory. A synthesizable code generator produces synthesizable code for a sender interface, storage, receiver interface, and other features that are specified by a programmer. The other features may reduce power consumption or improve timing. The code generator is used to efficiently produce different variations of FIFO memories.
申请公布号 US7630389(B1) 申请公布日期 2009.12.08
申请号 US20060399247 申请日期 2006.04.06
申请人 NVIDIA CORPORATION 发明人 ALFIERI ROBERT A.;OLIVEIRA MARCIO T.
分类号 H04L12/28 主分类号 H04L12/28
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