FLEXIBLE ARCHITECTURE DATA PROCESSING UNIT

摘要

Data processing unit (10) having a field programmable gate array (FPGA, 1) and input/output interfaces (11-16). A number of functional elements are implemented in the FPGA (1), such as: - at least one embedded processor (2); an microprocessor interface bus (29) connected to the at least one embedded processor (2); a switch fabric (9) connected to the microprocessor interface bus (29), in which the switch fabric (9) provides a connection with FIFO compatible data sources or destinations (7; 30; 32; 33; 34); and a peripheral interconnection bus (32) connected to switch fabric.