| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce the number of terminals of a receiver and to suppress power consumption in the receiver. <P>SOLUTION: The receiver converts differential signals into serial data strings, outputs them, generates a first clock having a frequency which is at least double the received basic clock signals and a second clock signal having an inverted phase, and generates and outputs first and second delay clock signals for which the first and second clock signals are respectively delayed for equal delay amounts. The receiver includes first and second flip-flops for fetching and outputting at least a part of data strings in synchronism with the first and second delay clock signals, and a delay amount adjustment part for receiving the output of the first flip-flop and the output of the second flip-flop and adjusting the delay amount in a delay part so that both of the output match or the output one clock cycle before of the first delay clock signal of the first flip-flop and the output of the second flip-flop match. <P>COPYRIGHT: (C)2010,JPO&INPIT |
