发明名称 A/D CONVERTING CIRCUIT AND SOLID-STATE IMAGING DEVICE
摘要 PROBLEM TO BE SOLVED: To permit the constitution of a clock generating circuit without providing with a buffer circuit for supplying power source. SOLUTION: A plurality of stages of converting circuit are connected to the clock generating circuit 110 to input a starting signal for starting the generation of the clock and an output signal from the converting circuit of a predetermined stages into one of the converting circuit while an element, whose impedance is changed in accordance with the magnitude of an objective analog signal which becomes the objective of conversion into a digital signal, is provided between neighbored conversion circuits mutually to generate the clock of a frequency in accordance with the magnitude of the objective analog signal. A counter 192 counts the clock generated by the clock generating circuit 110 and outputs the value of counting. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2009284388(A) 申请公布日期 2009.12.03
申请号 JP20080136355 申请日期 2008.05.26
申请人 OLYMPUS CORP;DENSO CORP 发明人 HAGIWARA YOSHIO
分类号 H03M1/50 主分类号 H03M1/50
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