发明名称 ACHIEVING BOTH LOCKING FAIRNESS AND LOCKING PERFORMANCE WITH SPIN LOCKS
摘要 <p>A method for implementing a spin lock in a system including a plurality of processing nodes, each node including at least one processor and a cache memory, the method including steps of: acquiring exclusivity to the cache memory; checking the availability of the spin lock; setting the spin lock to logical one if the spin lock is available; setting the spin lock to logical zero once processing is complete; and explicitly yielding the cache memory exclusivity. Yielding the cache memory exclusivity includes instructing the cache coherent hardware to mark the cache memory as non-exclusive. The cache memory is typically called level two cache.</p>
申请公布号 EP2126704(A2) 申请公布日期 2009.12.02
申请号 EP20080705921 申请日期 2008.01.15
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION IBM 发明人 SU, GONG
分类号 G06F12/00;G06F9/46;G06F9/52;G06F12/08 主分类号 G06F12/00
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