发明名称 Register state saving and restoring
摘要 <p>In a data processing apparatus 1 having registers 6, when a state saving trigger event occurs while a result value of a data processing operation is still to be written to a destination register then saving and restoring control circuitry 12 selects a state saving sequence defining a temporal order for saving register values to a backup data store 10. The sequence is selected to provide the destination register with a position within the sequence corresponding to a time after the result value has been written to the destination register. The register values are then saved to the backup data store 10 in the order of the selected state saving sequence. A similar technique can be used when a state restoring trigger event triggers loading of the data values from the backup data store 10 to the registers 6.</p>
申请公布号 GB0918298(D0) 申请公布日期 2009.12.02
申请号 GB20090018298 申请日期 2009.10.19
申请人 ARM LIMITED 发明人
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