发明名称 Frequency control system that stabilizes an output through both a counter and voltage-controlled oscillator via sampling a generated clock into four states
摘要 A frequency control system includes a voltage-controlled oscillator, a sampling circuit for sampling a clock signal produced by the oscillator for two consecutive transitions of an unstable incoming digital signal, and a frequency comparator for incrementing and decrementing a transition upcounter-downcounter controlling the oscillator. The system tolerates variation of the frequency of the incoming signal about a mean value, which has no effect on a clock signal to be extracted by means of a phase comparator or on the synthesized clock signal supplied by the oscillator if the incoming signal contains a high level of jitter and is supplied by a programmable frequency divider.
申请公布号 USRE41031(E1) 申请公布日期 2009.12.01
申请号 US20060367051 申请日期 2006.03.02
申请人 MAJOS JACQUES 发明人 MAJOS JACQUES
分类号 G06F1/04;H03L7/06;G06F1/08;G06F11/00;H03L7/087;H03L7/089;H03L7/091;H04L7/033 主分类号 G06F1/04
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