发明名称 TRANSFORMATION OF IC DESIGNS FOR FORMAL VERIFICATION
摘要 A memory is encoded with data that represents a reference IC design, a retimed IC design, and logical relationships, wherein at least one logical relationship describes combinational logic without reference to structural information, such as actual cells that have been instantiated in the IC designs. The logical relationships are used to instantiate logic described therein, and to define one or more black boxes as being functionally inverse of the logic. Each instantiated logic and its functionally inverse black box are thereafter added to the reference IC design to obtain a transformed reference IC design. A transformed retimed IC design is also obtained by addition of the instantiated logic(s) and functionally inverse black box(es) to the retimed IC design. These two transformed IC designs are then supplied to an equivalence checker, for formal verification.
申请公布号 US2009293028(A1) 申请公布日期 2009.11.26
申请号 US20090511987 申请日期 2009.07.29
申请人 HIRAOGLU MUZAFFER;JOSEF ZEPTER PETER WILHELM 发明人 HIRAOGLU MUZAFFER;JOSEF ZEPTER PETER WILHELM
分类号 G06F17/50 主分类号 G06F17/50
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